29. One Shot Pulse

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IshitaDey

November 4, 2025

Solving Approach

How do you plan to solve it?

Code

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Write your code here
    pulse<=rst?1'b0:((~prev) & sig_in);
    prev<=rst?1'b0:sig_in;
  end
endmodule

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