29. One Shot Pulse

How do you plan to solve it?

module rise_pulse (
    input  wire clk,
    input  wire rst,      // synchronous active-high reset
    input  wire sig_in,
    output reg  pulse
);

    reg prev;

    always @(posedge clk) begin
        if (rst) begin
            prev  <= 1'b0;
            pulse <= 1'b0;
        end
        else begin
            pulse <= sig_in & ~prev;  // rising edge detect
            prev  <= sig_in;
        end
    end

endmodule