29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in
  reg edgee;
  always @(posedge clk) begin
    // Write your code here

    prev<=sig_in;
    if (rst) begin
      prev<=1'b0;
      pulse<=1'b0;
    end else if (sig_in==1)
    begin 
      if (prev==1) begin
      pulse<=1'b0;
      end
      else begin
      pulse<=~pulse;
      prev<=1'b1;
      end
      end
    end
endmodule