29. One Shot Pulse

How do you plan to solve it?

// Module: rise_pulse
// Purpose: Generate a one-clock-wide pulse on rising edge of sig_in

module rise_pulse (
    input  wire clk,
    input  wire rst,
    input  wire sig_in,
    output reg  pulse
);

  // Internal register to store previous state of sig_in
  reg prev_sig;

  // Sequential logic block
  always @(posedge clk) begin
    if (rst) begin
      prev_sig <= 1'b0;   // Clear previous state
      pulse    <= 1'b0;   // No pulse during reset
    end
    else begin
      // Detect rising edge: current=1, previous=0
      pulse    <= sig_in & ~prev_sig;
      prev_sig <= sig_in;  // Update previous state
    end
  end

endmodule