29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in
  always @(posedge clk ) begin 
    if(rst)begin
        pulse<=0;
        prev<=0;
    end
    else begin
    prev<=sig_in;
    if(prev==0 && sig_in)
        pulse<=1;
    else 
        pulse<=0;
  end
  end
endmodule