29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Write your code here
    pulse <= sig_in & ~pulse & ~prev ? 1 : 0;
    prev <= sig_in;
    if (rst) prev <= 0;
    if (rst) pulse <= 0;

  end
endmodule