29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    if (rst)
      prev <= 0;
    else
      prev <= sig_in;
  end

  always @(posedge clk) begin 
    if (rst)
      pulse <= 0;
    else 
      pulse <= sig_in & (~prev);
  end
endmodule