29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,     
  input  wire sig_in,
  output reg  pulse
);
  reg prev;          

  always @(posedge clk) begin

  prev<=sig_in;
  if(rst) begin
  pulse<=0;
  prev<=0; end
  else begin
  if(sig_in && !prev)
   pulse<=1;
  if(pulse)
   pulse<=0;
  end
  end

  
endmodule