29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin
    // Write your code here
    prev <= sig_in;
    if(sig_in ==1 & prev ==0 & rst != 1) begin
      pulse <= 1;
    end
    else if(rst == 1) begin
      prev <= 0;
      pulse = 0;
    end
    else begin
      pulse <= 0;
    end
  
  end
endmodule