29. One Shot Pulse

Two different approaches

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk) begin

    pulse <= rst ? 1'b0 : ((~prev) & sig_in);

    prev  <= rst ? 1'b0 : sig_in;
  end
endmodule

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk ) begin
    // Write your code here
    if(rst) begin
      pulse <= 1'b0;
      prev <= 1'b0;
    end
    else begin
      if(sig_in == 1 && prev == 0) begin
        pulse <= 1'b1;

      end
      else begin
        pulse <= 1'b0;
      end
      prev <= sig_in;
    end
  end
endmodule