29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in
  reg rst_f;

  always @(posedge clk) begin
    // Write your code here
    prev <= sig_in;
    if(rst) begin
      pulse <= 1'b0;
      rst_f <= 1'b1;
    end
    else begin
      rst_f <= 1'b0;
      if(sig_in) begin
        if(~prev || rst_f) begin
          pulse <=1'b1;
        end
        else begin
          pulse <= 1'b0;
        end
      end
      else begin
        pulse <= 1'b0;
      end
    end
  end
endmodule