29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(
  input  wire clk,
  input  wire rst,      // synchronous active-high reset
  input  wire sig_in,
  output reg  pulse
);
  reg prev;             // previous sampled value of sig_in

  always @(posedge clk ) begin
    // Write your code here
    pulse <= rst ? 1'b00 : (~(prev)&sig_in); 
    prev <= rst ? 1'b00 : sig_in ; 
  end
endmodule