29. One Shot Pulse

How do you plan to solve it?

module rise_pulse (
    input  wire clk,
    input  wire rst,      // synchronous active-high reset
    input  wire sig_in,
    output reg  pulse
);

    reg sig_in_d;         // delayed (previous) value of sig_in

    always @(posedge clk) begin
        if (rst) begin
            sig_in_d <= 1'b0;
            pulse    <= 1'b0;
        end else begin
            // rising edge detection
            pulse    <= sig_in & ~sig_in_d;
            sig_in_d <= sig_in;
        end
    end

endmodule