29. One Shot Pulse

How do you plan to solve it?

module rise_pulse(input wire clk, input wire rst, input wire sig_in, output reg pulse);
reg prev;            
always @(posedge clk) begin
  pulse <= rst ? 1'b0 : ((~prev) & sig_in);
  prev  <= rst ? 1'b0 : sig_in;
  end
endmodule