Testbench Code

`timescale 1ns/1ps
module tb_open_source_line;
  reg  drive_high;
  wire line;
  wire expected_line;
  wire mismatch;

  open_source_line dut(.drive_high(drive_high), .line(line));

  assign expected_line = drive_high ? 1'b1 : 1'b0;
  assign mismatch      = (line !== expected_line);

  integer TOTAL_TEST_CASES, TOTAL_PASSED_TEST_CASES, TOTAL_FAILED_TEST_CASES;
  reg [8*20-1:0] tc_name;

  initial begin
    $dumpfile("tb_open_source_line.vcd");
    $dumpvars(0, drive_high, line, expected_line, mismatch);
  end

  task run_case;
    input dh;
    input [8*20-1:0] name;
    begin
      drive_high = dh; tc_name = name; #1;
      $display("CASE=%s : drive_high=%0b | line=%0b expected_line=%0b %s",
               tc_name, drive_high, line, expected_line,
               mismatch ? "MISMATCH" : "OK");
      TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
      if (!mismatch) TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
      else begin
        TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
        $display("  FAILED INPUTS: drive_high=%0b  EXPECTED: expected_line=%0b",
                 drive_high, expected_line);
      end
      #4;
    end
  endtask

  initial begin
    TOTAL_TEST_CASES = 0; TOTAL_PASSED_TEST_CASES = 0; TOTAL_FAILED_TEST_CASES = 0;

    run_case(0, "released_idle_low");   // expect 0
    run_case(1, "driven_high");         // expect 1

    $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
    $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
    $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
    $display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

    $finish;
  end
endmodule