Problem: PNP NAND Gate. Solve this hands-on electronics task on EWskills.

If either input is LOW, the corresponding PNP transistor turns ON and pulls Y HIGH. Both transistors turn OFF only when both inputs are HIGH. Y = (A · B)'

26. PNP NAND Gate

Implement a 2-input NAND gate using PNP transistors so that output Y becomes LOW only when both inputs are HIGH.

Constraints

Inputs: A, B
Output: Y
Supply: 5 V
Use PNP transistors and resistors.
Do not use NPN transistors, MOSFETs, diodes, switches, or ready-made logic gates.

Behavioral Reference

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

Need Help? Refer to the Quick Guide below

Transistors behave like controlled switches. A logic output is determined by whether the transistor network connects Y to VDD or ground.

1. Basic Concept

Transistor	Turns ON for	Usually connects Y toward
NPN	HIGH input	Ground
NMOS	HIGH input	Ground
PNP	LOW input	VDD
PMOS	LOW input	VDD

Remember:

NPN / NMOS → Active HIGH

PNP / PMOS → Active LOW

BJT and MOSFET Inverter Circuits Comparison:

Schematic comparison of NPN, PNP, NMOS, and PMOS transistor inverter and buffer configurations."

2. Read the Output Path

Pull-down logic

VDD → Pull-up resistor → Y → NPN/NMOS network → Ground

Network conducts → Y = 0
Network is open → Y = 1

NMOS transistor inverter logic gate schematic diagram with pull-up resistor.

Pull-up logic

VDD → PNP/PMOS network → Y → Pull-down resistor → Ground

Network conducts → Y = 1
Network is open → Y = 0

PMOS transistor buffer logic schematic diagram with pull-down resistor.

3. Resistor-Loaded Gate Reference

Device network	NOT	NAND	NOR
NPN / NMOS pull-down	One transistor	Series	Parallel
PNP / PMOS pull-up	One transistor	Parallel	Series

Key expressions

NOT: Y = A'

NAND: Y = (A · B)'

NOR: Y = (A + B)'

NMOS and PMOS Basic Logic Gate Implementations (NOT, NAND, NOR):

Schematic comparison of basic NMOS and PMOS logic gates including NOT, NAND, and NOR configurations.

4. Building AND and OR

A resistor-loaded transistor stage commonly produces NAND or NOR. Add an inverter to obtain AND or OR.

AND

A, B → NAND stage → X → Inverter → Y

X = (A · B)'

Y = X' = A · B

A, B → NOR stage → X → Inverter → Y

X = (A + B)'

Y = X' = A + B

For example, Two-Stage AND Gate (using NAND and NOT):

2-input RTL BJT NAND and AND logic gate schematic diagram with dual outputs.

5. CMOS Logic

CMOS uses two complementary transistor networks.

PMOS Pull-Up network connects Y to VDD
NMOS Pull-Down network connects Y to ground
Their series and parallel arrangements are opposite

2-input CMOS NAND logic gate transistor schematic diagram.

CMOS inverter

A	PMOS	NMOS	Y
0	ON	OFF	1
1	OFF	ON	0

CMOS NAND and NOR

Gate	PMOS network	NMOS network
NAND	Parallel	Series
NOR	Series	Parallel

6. Three-Input Gates

Gate	PMOS arrangement	NMOS arrangement
3-input NAND	Parallel	Series
3-input NOR	Series	Parallel

3-input NAND: Y = (A · B · C)'

3-input NOR: Y = (A + B + C)'

3-input CMOS NAND and NOR logic gate transistor schematic comparison.

7. XOR and XNOR

A	B	XOR	XNOR
0	0	0	1
0	1	1	0
1	0	1	0
1	1	0	1

XOR

HIGH when inputs are different.

Y = A' · B + A · B'

XNOR

HIGH when inputs are equal.

Y = A' · B' + A · B

CMOS transistor-level XOR and XNOR logic gate schematic diagram with complementary outputs.

8. BJT and CMOS Comparison

Feature	BJT Logic	CMOS Logic
Input control	Base current	Gate voltage
Main devices	NPN and PNP	NMOS and PMOS
Static power	Usually higher	Usually lower
Input resistance	Lower	Very high
Circuit structure	Resistors and transistors	Complementary transistor networks
Common use	Drivers and simple gates	Digital ICs and processors