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48. Safe MUX

module safe_mux2 (
    input  [7:0] a,
    input  [7:0] b,
    input        sel,
    output reg [7:0] y,
    output reg       sel_unknown
);
    always @* begin
        y           = 8'h00;
        sel_unknown = 1'b0;

        if (sel === 1'b0) begin
            y = a;
        end else if (sel === 1'b1) begin
            y = b;
        end else begin
            sel_unknown = 1'b1;
            y = 8'h00;
        end
    end
endmodule

💡Remember

  • === / !== perform 4-state comparisons—perfect for handling x/z in simulation.
  • Default assignments keep the combinational block latch-free.