22. Shared Line using wor

Two alarm sources share a siren line. If either asserts, siren must be 1.

Module: alarm_siren
Inputs: alarm1, alarm2
Output: siren (use wor so multiple drivers OR together)

Please login to run the code.

Testbench Code

`timescale 1ns/1ps
module tb_alarm_siren;
  reg  alarm1, alarm2;
  wire siren;
  wire expected_siren;
  wire mismatch;

  alarm_siren dut(.alarm1(alarm1), .alarm2(alarm2), .siren(siren));

  assign expected_siren = alarm1 | alarm2;
  assign mismatch       = (siren !== expected_siren);

  integer TOTAL_TEST_CASES, TOTAL_PASSED_TEST_CASES, TOTAL_FAILED_TEST_CASES;
  reg [8*20-1:0] tc_name;

  initial begin
    $dumpfile("tb_alarm_siren.vcd");
    $dumpvars(0, alarm1, alarm2, siren, expected_siren, mismatch);
  end

  task run_case;
    input a1, a2;
    input [8*20-1:0] name;
    begin
      alarm1 = a1; alarm2 = a2; tc_name = name; #1;
      $display("CASE=%s : a1=%0b a2=%0b | siren=%0b expected_siren=%0b %s",
               tc_name, alarm1, alarm2, siren, expected_siren,
               mismatch ? "MISMATCH" : "OK");
      TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
      if (!mismatch) TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
      else begin
        TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
        $display("  FAILED INPUTS: a1=%0b a2=%0b  EXPECTED: expected_siren=%0b",
                 alarm1, alarm2, expected_siren);
      end
      #4;
    end
  endtask

  initial begin
    TOTAL_TEST_CASES = 0; TOTAL_PASSED_TEST_CASES = 0; TOTAL_FAILED_TEST_CASES = 0;

    run_case(0,0,"both_idle");
    run_case(1,0,"alarm1_only");
    run_case(0,1,"alarm2_only");
    run_case(1,1,"both_active");

    $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
    $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
    $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
    $display("ALL_TEST_CASES_PASSED=%s", (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

    $finish;
  end
endmodule