45. Signed vs Unsigned Compare

module signed_thresh(
  input  wire [7:0] sample,
  input  wire [7:0] thresh,
  output wire       gt_unsigned,
  output wire       gt_signed
);
  assign gt_unsigned = (sample > thresh);
  assign gt_signed   = ($signed(sample) > $signed(thresh));
endmodule

💡 Remember

In Verilog, vectors are unsigned by default; relational operators use the operands’ signedness.
Casting with $signed(expr) interprets the bit pattern as two’s-complement and performs a signed comparison.
Equality ==/!= is unaffected by signedness (but X/Z still matter); ordering operators (<, <=, >, >=) are where signed vs unsigned diverge.
Typical surprises: 8'h80 is 128 unsigned but −128 signed; 8'hFF is 255 unsigned but −1 signed.
When sizes differ, Verilog self-determines a common size; keep both sides same width to avoid accidental extension rules masking bugs.