45. Signed vs Unsigned Compare

How do you plan to solve it?

/*Write your code here*/
module signed_thresh(sample,thresh,gt_signed,gt_unsigned);
input [7:0]sample,thresh;
output reg gt_unsigned=0,gt_signed=0;
reg signed [7:0]si_sample,si_thresh;
always@(*)begin
        gt_unsigned=sample>thresh?1:0;
        si_sample=sample;
        si_thresh=thresh;
        gt_signed=si_sample>si_thresh?1:0;

    end

endmodule