45. Signed vs Unsigned Compare

How do you plan to solve it?

/*Write your code here*/
module signed_thresh
(
    input wire [7:0] sample,thresh,
    output wire gt_signed,gt_unsigned
);
    wire t0,t1;
    assign gt_unsigned = sample > thresh ? 1 : 0;
    //assign t0 = sample > 0 ? sample : -sample; 
    //assign t1 = thresh > 0 ? thresh : -thresh;
    //assign gt_signed = t0 > t1 ?  1 : 0;
    assign gt_signed = $signed(sample) > $signed(thresh) ? 1 : 0;
endmodule