45. Signed vs Unsigned Compare

How do you plan to solve it?

/*Write your code here*/

module signed_thresh (
    input [7:0] sample,thresh,
    output gt_unsigned,gt_signed
);

assign gt_unsigned = (sample > thresh);

wire signed [7:0] a1,a2;
assign a1 = sample;
assign a2 = thresh ;

assign gt_signed = (a1 > a2); 


endmodule