SR Latch

Question

Problem: SR Latch. Solve this hands-on electronics task on EWskills.

Accepted Answer

Behavioral

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    reg Q_reg;
    reg Qn_reg;

    always @(*) begin
        if (S && R) begin
            Q_reg  = 1'b0;
            Qn_reg = 1'b1;
        end else if (S && !R) begin
            Q_reg  = 1'b1;
            Qn_reg = 1'b0;
        end else if (!S && R) begin
            Q_reg  = 1'b0;
            Qn_reg = 1'b1;
        end
    end

    assign Q  = Q_reg;
    assign Qn = Qn_reg;
endmodule

Structural

module sr_latch_nor (
    input  S,
    input  R,
    output Q,
    output Qn
);
    wire nR, S_eff;

    not u_invR(nR, R);           // nR = ~R
    and u_setg(S_eff, S, nR);    // S_eff = S & ~R  (suppress set when R=1)

    nor uQ (Q , R    , Qn);      // Q  = ~(R | Qn)
    nor uQn(Qn, S_eff, Q );      // Qn = ~(S_eff | Q)

endmodule

💡Remember

Procedural:
- Procedural modeling avoids explicit combinational feedback loops and synthesizes cleanly.
- Leaving assignments untouched when S=R=0 creates the level-sensitive storage element.
- Mapping S=R=1 to Reset prevents X propagation and keeps behavior deterministic.
- No reliance on initial values; the environment establishes the first known state.
Structural:
- Structural style mirrors the textbook cross-coupled NOR latch using continuous assignments.
- Useful for understanding feedback behavior and timing sensitivity in simulation.
- Many synthesis flows flag combinational loops; prefer the behavioral model for synthesis.
- With S=R=1, both nodes are driven low in ideal NOR logic; deterministic handling in system-level specs is recommended.

73. SR Latch