73. SR Latch

Design an active-high SR latch that behaves like a cross-coupled NOR latch with deterministic handling of the illegal input combination.

Requirements

• Module: sr_latch_nor
• Ports:
  • Inputs:
    • S
    • R
  • Outputs:
    • Q
    • Qn
• Functional behavior
  • S=1, R=0 → Q=1, Qn=0 (Set)
  • S=0, R=1 → Q=0, Qn=1 (Reset)
  • S=0, R=0 → Hold previous state
  • S=1, R=1 → Treated as Reset (deterministic mapping)
• Modeling constraints
  • Use procedural modeling (always @(*)) to infer level-sensitive storage (no clocks).
  • On S=0, R=0, leave outputs unassigned to hold state.
  • Qn must remain the logical complement of Q.

Behaviour / Worked Example

Starting from reset:

1. R=1,S=0 → Q=0,Qn=1
2. R=0,S=0 → hold Q=0,Qn=1
3. R=0,S=1 → Q=1,Qn=0
4. R=0,S=0 → hold Q=1,Qn=0
5. R=1,S=1 → treated as Reset → Q=0,Qn=1
6. R=0,S=0 → hold Q=0,Qn=1