74. Gated SR Latch

Design a level-sensitive SR latch with an enable input. When enabled, it behaves like an active-high SR latch with deterministic handling of the illegal input combination; when disabled, it holds its current state.

Requirements

• Module: sr_latch_enable
• Ports:
  • Inputs:
    • EN
    • S
    • R
  • Outputs:
    • Q
    • Qn
• Functional behavior
  • If EN=1:
    • S=1, R=0 → Set: Q=1, Qn=0
    • S=0, R=1 → Reset: Q=0, Qn=1
    • S=1, R=1 → Illegal; treat as Reset: Q=0, Qn=1
    • S=0, R=0 → Hold
  • If EN=0:
    • Ignore S/R and hold previous state
• Modeling constraints
  • Use procedural modeling (always @(*)) to infer level-sensitive storage.
  • For EN=1, use priority reset > set > hold.
  • Do not rely on register initialization; holding state is created by omitting assignments in the hold paths.

Behaviour / Worked Example

From a reset state (Q=0,Qn=1):

1. EN=1,S=0,R=0 → hold Q=0,Qn=1
2. EN=1,S=1,R=0 → set Q=1,Qn=0
3. EN=0,S=0,R=1 → hold (enable low) Q=1,Qn=0
4. EN=1,S=0,R=1 → reset Q=0,Qn=1
5. EN=1,S=1,R=1 → illegal; treated as reset Q=0,Qn=1
6. EN=1,S=0,R=0 → hold Q=0,Qn=1