Problem: Tri-State Buffer. Solve this hands-on electronics task on EWskills.

module tribuf_prim ( input a, input en, output y ); bufif1 g_buf (y, a, en); endmodule 💡Remember bufif1 = transparent when enable=1 , else drives z . bufif0 = transparent when enable=0 , else drives z . Tri-state buffers are used to share a bus; only one driver may be enabled at a time. If en=x or z , output may become x/z depending on a .

37. Tri-State Buffer

Implement a tri-state buffer:

When en=1, output y = a.
When en=0, output y = z.

Requirements

Module: tribuf_prim
Inputs: a, en
Output: y
Use the built-in primitive bufif1 (no assign, no always).

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Verilog Primitives or Inbuilt gates & switches

n_input gates	n_output_gates	Three-state gates	Pull gates	MOS switches	Bidirectional switches
and	buf	bufif0	pulldown	cmos	rtran
nand	not	bufif1	pullup	nmos	rtranif0
nor		notif0		pmos	rtranif1
or		notif1		rcmos	tran
xnor				rnmos	tranif0
xor				rpmos	tranif1

n-input Gates

Basic combinational logic gates with n inputs (2 or more).

and, nand, or, nor, xor, xnor
Used to build basic Boolean functions directly.
Synthesizable (mapped to standard logic cells).

n-output Gates

Single-input, multiple-output primitives.

buf → buffer (copies input to output(s)).
not → inverter (logical NOT).
Multiple outputs can be driven by a single source.

Three-State Gates

Output can be 0, 1, or high-impedance (Z).

bufif0, bufif1 → buffer with active-low or active-high enable.
notif0, notif1 → inverter with active-low or active-high enable.
Commonly used for tri-state buses.

Pull Gates

Provide weak constant logic values.

pullup → weak ‘1’.
pulldown → weak ‘0’.
Often used for default bus values or test benches.
Synthesizers usually replace them with explicit tie cells.

MOS Switches

Model ideal MOS transistors (digital switch-level).

nmos, pmos → NMOS/PMOS transistors.
cmos → CMOS transmission gate (p- and n-MOS pair).
rnmos, rpmos, rcmos → resistive versions (weak drive strength).
Mostly for switch-level simulation, not synthesizable in RTL.

Bidirectional Switches

Transmission gates passing signals both ways.

tran → bidirectional wire connection.
rtran → resistive bidirectional.
tranif0/tranif1 → conditional pass switch, controlled by enable (low/high).
rtranif0/rtranif1 → resistive conditional pass switch.
Used in switch-level modeling, not synthesizable.

👉 Rule of thumb for RTL design:

Use n-input gates and n-output gates sparingly (structural design).
Use three-state gates for I/O buffers (top-level ports).
Avoid MOS and bidirectional switches in RTL (simulation-only).