Testbench Code

`timescale 1ns/1ps

module tb_tribuf_prim;
    // 1) Inputs
    reg a, en;

    // 2) DUT outputs
    wire y;

    // 3) Expected (prefixed expected_)
    reg expected_y;

    // 4) Mismatch (HIGH on fail)
    wire mismatch = (y !== expected_y);

    // Counters
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // VCD limit
    integer VCD_MAX_CASES = 32;

    // DUT
    tribuf_prim dut(.a(a), .en(en), .y(y));

    // VCD dump (Inputs -> Outputs -> Expected -> Mismatch)
    initial begin
        $dumpfile("tb_tribuf_prim.vcd");
        $dumpvars(0,
            tb_tribuf_prim.a, tb_tribuf_prim.en,    // Inputs
            tb_tribuf_prim.y,                       // Output
            tb_tribuf_prim.expected_y,              // Expected
            tb_tribuf_prim.mismatch                 // Mismatch
        );
        $dumpon; // start at time 0
    end

    // Helper for pretty-printing 4-state values
    function [7*8-1:0] bit2s;
        input bitval;
        begin
            if      (bitval === 1'b0) bit2s = "0";
            else if (bitval === 1'b1) bit2s = "1";
            else if (bitval === 1'bx) bit2s = "x";
            else                      bit2s = "z";
        end
    endfunction

    // Reference model for bufif1
    task compute_expected;
        input ta, ten;
        begin
            if (ten === 1'b1) begin
                if      (ta === 1'b0) expected_y = 1'b0;
                else if (ta === 1'b1) expected_y = 1'b1;
                else                  expected_y = 1'bx; // a = x/z -> unknown
            end
            else if (ten === 1'b0) begin
                expected_y = 1'bz; // disabled -> high-Z
            end
            else begin
                expected_y = 1'bx; // enable unknown -> unknown
            end
        end
    endtask

    // Apply + check (EXPECTED FIRST -> WAIT -> COMPARE)
    task apply_and_check;
        input ta, ten;
        begin
            a  = ta;
            en = ten;

            compute_expected(ta, ten); // expected first
            #1;                        // let DUT settle

            TOTAL_TEST_CASES++;
            if (!mismatch) TOTAL_PASSED_TEST_CASES++; else TOTAL_FAILED_TEST_CASES++;

            $display(" a=%s en=%s | y=%s | expected=%s | mismatch=%0d",
                     bit2s(a), bit2s(en), bit2s(y), bit2s(expected_y), mismatch);

            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
        end
    endtask

    initial begin
        $display(" a en | y | expected | mismatch");
        $display("--------------------------------");

        // Directed tests (<= 20 rows total)
        apply_and_check(1'b0, 1'b0); // -> z
        apply_and_check(1'b1, 1'b0); // -> z
        apply_and_check(1'b0, 1'b1); // -> 0
        apply_and_check(1'b1, 1'b1); // -> 1

        // X/Z cases
        apply_and_check(1'bx, 1'b1); // -> x
        apply_and_check(1'bz, 1'b1); // -> x
        apply_and_check(1'b1, 1'bx); // -> x
        apply_and_check(1'b0, 1'bx); // -> x
        apply_and_check(1'b1, 1'bz); // -> x
        apply_and_check(1'b0, 1'bz); // -> x

        // Summary
        $display("--------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule