/*Write your code here*/
module univ_barrel8(
input [7:0] x,
input [2:0] sh,
input [2:0] mode,
output reg [7:0] y
);
wire [7:0] lsl = x << sh;
wire [7:0] lsr = x >> sh;
wire [7:0] asr = $signed(x) >>> sh;
wire [7:0] rol = (x << sh) | (x >> (8-sh));
wire [7:0] ror = (x >> sh) | (x << (8-sh));
always@(*)begin
case(mode)
3'b000 : y = x; //PASS
3'b001 : y = lsl; //LSL (logical left)
3'b010 : y = lsr; // LSR (logical right)
3'b011 : y = asr; //ASR (arithmetic right, sign-extend)
3'b100 : y = rol; //ROL (rotate left)
3'b101 : y = ror; // ROR (rotate right)
default : y = x;
endcase
end
endmodule