module univ_barrel8 (
input [7:0] x,
input [2:0] sh,
input [2:0] mode,
output [7:0] y
);
// Explicit sign extension
wire signed [8:0] sx_ext;
assign sx_ext = {x[7], x};
// Arithmetic shift result stored in a wire
wire signed [8:0] asr_res;
assign asr_res = sx_ext >>> sh;
assign y =
(mode == 3'b000) ? x :
(mode == 3'b001) ? (x << sh) :
(mode == 3'b010) ? (x >> sh) :
(mode == 3'b011) ? asr_res[7:0] : // ✅ now legal
(mode == 3'b100) ? ((x << sh) | (x >> (8 - sh))) :
(mode == 3'b101) ? ((x >> sh) | (x << (8 - sh))) :
x; // reserved → PASS
endmodule