module univ_barrel8(
input [7:0] x,
input [2:0] sh,mode,
output reg [7:0] y
);
always @(*) begin
case(mode)
3'b000: y = x;
// LSL
3'b001: y = x << sh;
// LSR
3'b010: y = x >> sh;
// ASR
3'b011: y = $signed(x) >>> sh;
// ROL
3'b100: y = (x << sh) | (x >> (8 - sh));
// ROR
3'b101: y = (x >> sh) | (x << (8 - sh));
default: y = x;
endcase
end
endmodule