/*Write your code here*/
module univ_barrel8 (
input [7:0] x,
input [2:0] sh,
input [2:0] mode,
output reg [7:0] y
);
always @* begin
case (mode)
3'b000 : y = x;
3'b001 : y = x << sh;
3'b010 : y = x >> sh;
3'b011 : y = $signed(x) >>> sh;
3'b100 : y = (x << sh) | (x >> (8 - sh)); // ROL
3'b101 : y = (x >> sh) | (x << (8 - sh)); // ROR
default : y = x;
endcase
end
endmodule