How do you plan to solve it?
/*Write your code here*/
module univ_barrel8(
input [7:0] x,
input [2:0] sh,
input [2:0] mode,
output reg [7:0] y
);
always @* begin
case (mode)
3'b000: y = x; // → PASS
3'b001: y = (x << sh) & 8'hFF; // → LSL (logical left)
3'b010: y = (x >> sh); // → LSR (logical right)
3'b011: y = $signed(x) >>> sh; // → ASR (arithmetic right, sign-extend)
3'b100: y = ((x << sh) | (x >> (8 - sh))) & 8'hFF; // → ROL (rotate left)
3'b101: y = ((x >> sh) | (x << (8 - sh))) & 8'hFF; // → ROR (rotate right)
// 3'b110: y = x;
// 3'b111: y = x; // → reserved (treat as PASS in reference)
default: y = x; // → reserved (treat as PASS in reference)
endcase
end
endmodule