module sat_add8_wrap (
input [7:0] a,
input [7:0] b,
output reg [7:0] sum,
output reg carry
);
task sat_add8;
input [7:0] ta, tb;
output [7:0] tsum;
output tcarry;
reg [8:0] raw;
begin
raw = ta + tb;
tcarry = raw[8];
tsum = tcarry ? 8'hFF : raw[7:0];
end
endtask
reg [7:0] s;
reg c;
always @* begin
sat_add8(a, b, s, c);
sum = s;
carry = c;
end
endmodule
💡Remember
- Tasks can return multiple results via
output args — perfect for (sum, carry). - Call tasks from
always @* for combinational behavior; drive all outputs to avoid latches. - This pattern cleanly separates algorithm (task) from wiring (module).