How do you plan to solve it?
module sat_add8_wrap(
input wire [7:0] a,
input wire [7:0] b,
output reg [7:0] sum,
output reg carry
);
// -------- Provided task (DO NOT MODIFY) --------
task sat_add8(
input [7:0] ta, tb,
output [7:0] tsum,
output tcarry
);
reg [8:0] raw;
begin
raw = ta + tb; // 9-bit addition
tcarry = raw[8]; // unsigned carry-out
tsum = tcarry ? 8'hFF : raw[7:0]; // saturate to 0xFF
end
endtask
reg [7:0] s;
reg c;
// Use the task
always @(*) begin
sat_add8(a, b, s, c); // call the provided task
sum = s; // drive module outputs
carry = c;
end
endmodule