12. Vector Bitwise Operators

We will use the bitwise binary operators AND "&", OR "|", XOR "^", and XNOR "~^", with A and B as inputs, to produce the required information for each output.

One important thing is the need to use packed arrays "[dim:0]vec_name" instead of unpacked arrays "vec_name[dim:0] if you are used Verilog, 
since ports can only be unpacked arrays in SystemVerilog.

/* bitwise_ops_demo module presents the results of
 * the following bitwise operations with A and B (4-bits each)
 * [3:0]AND_OUT = bitwise AND of A and B
 * [3:0]OR_OUT = bitwise OR of A and B
 * [3:0]XOR_OUT = bitwise XOR of A and B
 * [3:0]XNOR_OUT = bitwise XNOR of A and B
 */

module bitwise_ops_demo (
    input [3:0]A,
    input [3:0]B,
    output [3:0]AND_OUT,
    output [3:0]OR_OUT,
    output [3:0]XOR_OUT,
    output [3:0]XNOR_OUT
);
    assign AND_OUT = A & B;
    assign OR_OUT = A | B;
    assign XOR_OUT = A ^ B;
    assign XNOR_OUT = A ~^ B;
endmodule