11. Vector Concatenation

Design a combinational module named concat8_packer that packs four inputs into a single 8-bit output according to the exact bit layout below.

Requirements

Module name: concat8_packer
Inputs:
- A[3:0] (4-bit)
- B[1:0] (2-bit)
- C (1-bit)
- D (1-bit)
Output:
- OUT[7:0] (8-bit)

Mapping (exact bit layout)

`OUT` bit range	What goes there (left→right = MSB→LSB)	Width
`[7:4]`	`A[3:0]` (preserve order: `A[3]`→MSB)	4
`[3:2]`	`B[1:0]`	2
`[1]`	`~C` (bitwise NOT of `C`)	1
`[0]`	`D`	1

Example

If A=4'b1101, B=2'b01, C=1'b0, D=1'b1 → OUT = 8'b1101_01_1_1 = 8'hD7.

Please login to run the code.

Testbench Code

`timescale 1ns/1ps

module tb_concat8_packer;
    // Inputs
    reg  [3:0] A;
    reg  [1:0] B;
    reg        C;
    reg        D;

    // DUT output
    wire [7:0] OUT;

    // Expected output
    reg  [7:0] expected_OUT;

    // Mismatch signal
    wire mismatch = (OUT !== expected_OUT);

    // Counters
    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // Instantiate DUT
    concat8_packer dut (
        .A(A), .B(B), .C(C), .D(D), .OUT(OUT)
    );

    // VCD dump (Inputs → Output → Expected → mismatch)
    initial begin
        $dumpfile("tb_concat8_packer.vcd");
        $dumpvars(0,
            tb_concat8_packer.A,
            tb_concat8_packer.B,
            tb_concat8_packer.C,
            tb_concat8_packer.D,
            tb_concat8_packer.OUT,
            tb_concat8_packer.expected_OUT,
            tb_concat8_packer.mismatch
        );
    end

    // Golden computation per spec
    task compute_expected;
        input [3:0] tA;
        input [1:0] tB;
        input       tC, tD;
        begin
            expected_OUT = {
                tA[3:0],  // [7:4]
                tB[1:0],  // [3:2]
                ~tC,      // [1]
                tD        // [0]
            };
        end
    endtask

    task run_one;
        input [3:0] tA;
        input [1:0] tB;
        input       tC, tD;
        begin
            A = tA; B = tB; C = tC; D = tD;
            compute_expected(tA, tB, tC, tD);
            #1;
            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            end else begin
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
                $display("FAILED: A=%b B=%b C=%b D=%b | OUT=%h expected=%h mismatch=%b",
                          A, B, C, D, OUT, expected_OUT, mismatch);
            end
        end
    endtask

    integer i;
    initial begin
        // Directed cases (updated example)
        run_one(4'b1101, 2'b01, 1'b0, 1'b1); // expect 8'hD7
        run_one(4'b0000, 2'b00, 1'b0, 1'b0);
        run_one(4'b1111, 2'b11, 1'b1, 1'b1);
        run_one(4'b1010, 2'b10, 1'b0, 1'b0);
        run_one(4'b0101, 2'b01, 1'b1, 1'b0);

        // Limited randomized coverage (≤ 20 iterations)
        for (i = 0; i < 20; i = i + 1) begin
            run_one($random, $random, $random, $random);
        end

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule