How do you plan to solve it?
module bitwise_ops_demo ( input [3:0] A,B, output reg [3:0] AND_OUT,OR_OUT,XOR_OUT,XNOR_OUT); always @(*) begin AND_OUT = A&B; OR_OUT = A|B; XOR_OUT = A^B; XNOR_OUT = A^~B; end endmodule