Vector Bitwise Operators

November 25, 2025

Solving Approach

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The approach is to apply Verilog’s bitwise operators directly to the input vectors and assign each corresponding result to a separate output to clearly demonstrate AND, OR, XOR, and XNOR operations.

Code

/*Write your code here*/

module bitwise_ops_demo(
    input [3:0] A,
    input [3:0] B,
    output [3:0] AND_OUT,
    output [3:0] OR_OUT,
    output [3:0] XOR_OUT,
    output [3:0] XNOR_OUT
);

assign AND_OUT = A & B;
assign OR_OUT = A | B;
assign XOR_OUT = A ^ B;
assign XNOR_OUT = A ~^ B;

endmodule

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Testbench Code

`timescale 1ns/1ps

module tb_bitwise_ops_demo;
    // Inputs
    reg  [3:0] A, B;

    // DUT outputs
    wire [3:0] AND_OUT, OR_OUT, XOR_OUT, XNOR_OUT;

    // Expected outputs
    reg  [3:0] expected_and, expected_or, expected_xor, expected_xnor;

    // Consolidated mismatch for waveform/debug
    wire mismatch_and, mismatch_or, mismatch_xor, mismatch_xnor;
    assign mismatch_and  = (AND_OUT  !== expected_and);
    assign mismatch_or   = (OR_OUT   !== expected_or);
    assign mismatch_xor  = (XOR_OUT  !== expected_xor);
    assign mismatch_xnor = (XNOR_OUT !== expected_xnor);
    wire mismatch = mismatch_and | mismatch_or | mismatch_xor | mismatch_xnor;

    // Simple counters
    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // DUT
    bitwise_ops_demo dut (
        .A(A), .B(B),
        .AND_OUT(AND_OUT), .OR_OUT(OR_OUT),
        .XOR_OUT(XOR_OUT), .XNOR_OUT(XNOR_OUT)
    );

    // VCD: dump only inputs, outputs, expected, and mismatch signals
    initial begin
        $dumpfile("tb_bitwise_ops_demo.vcd");
        $dumpvars(0,
            tb_bitwise_ops_demo.A, tb_bitwise_ops_demo.B,                        // inputs
            tb_bitwise_ops_demo.AND_OUT, tb_bitwise_ops_demo.OR_OUT,             // outputs
            tb_bitwise_ops_demo.XOR_OUT, tb_bitwise_ops_demo.XNOR_OUT,
            tb_bitwise_ops_demo.expected_and, tb_bitwise_ops_demo.expected_or,   // expected
            tb_bitwise_ops_demo.expected_xor, tb_bitwise_ops_demo.expected_xnor,
            tb_bitwise_ops_demo.mismatch                                         // consolidated flag
        );
    end

    // One test transaction
    task run_one;
        input [3:0] tA, tB;
        begin
            A = tA; B = tB;
            expected_and  = tA & tB;
            expected_or   = tA | tB;
            expected_xor  = tA ^ tB;
            expected_xnor = ~(tA ^ tB);
            #1;
            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;

            if (!mismatch) begin
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            end else begin
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
                $display("FAILED: A=%b B=%b | AND=%b OR=%b XOR=%b XNOR=%b | EXP AND=%b OR=%b XOR=%b XNOR=%b",
                         A,B,AND_OUT,OR_OUT,XOR_OUT,XNOR_OUT,
                         expected_and,expected_or,expected_xor,expected_xnor);
            end
        end
    endtask

    integer i;
    initial begin
        // Directed cases
        run_one(4'b1010, 4'b1100); // example above
        run_one(4'hF, 4'h0);
        run_one(4'hA, 4'h5);
        run_one(4'h3, 4'hC);

        // Randomized cases (Verilog-2005 friendly; truncation gives 4-bit)
        for (i=0; i<20; i=i+1) begin
            run_one($random, $random);
        end

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");
        $finish;
    end
endmodule