74. Asynchronous Counters

A counter is a sequential circuit that moves through a fixed sequence of binary states.

• Each active clock edge may advance the stored state according to the counter logic.
• Flip-flops store the count.
• An n-bit binary counter has 2ⁿ possible states.

Counters are used for:

• Counting events
• Frequency division
• Timing generation
• Sequence control
• Address generation

An asynchronous up counter counts from a smaller value to a larger value.

For a 3-bit counter:

000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000

In an asynchronous counter, only the first flip-flop receives the external clock. Each remaining flip-flop receives its clock from the previous stage.

Circuit Connections

For positive-edge-triggered T flip-flops:

• T0 = T1 = T2 = 1
• External CLK is connected to FF0.
• ~Q0 is connected to the clock of FF1.
• ~Q1 is connected to the clock of FF2.

Fig. 1: 3-bit Asynchronous Up Counter

Working

• Q0 toggles on every rising clock edge.
• Q1 toggles when Q0 changes from 1 → 0, producing a rising edge at ~Q0.
• Q2 toggles when Q1 changes from 1 → 0.
• After the ripple transitions settle, the output count has increased by one.

Table 1: Asynchronous Up-Counter Sequence

An asynchronous down counter counts from a larger value to a smaller value.

For a 3-bit counter:

111 → 110 → 101 → 100 → 011 → 010 → 001 → 000 → 111

Circuit Connections

For positive-edge-triggered T flip-flops:

• T0 = T1 = T2 = 1
• External CLK is connected to FF0.
• Q0 is connected to the clock of FF1.
• Q1 is connected to the clock of FF2.

Fig. 2: 3-bit Asynchronous Down Counter

Working

• Q0 toggles on every rising clock edge.
• Q1 toggles when Q0 changes from 0 → 1.
• Q2 toggles when Q1 changes from 0 → 1.
• After the ripple transitions settle, the output count has decreased by one.

Table 2: Asynchronous Down-Counter Sequence

The counting direction depends on three circuit choices:

• Flip-flop triggering edge
• Previous-stage output connected to the next clock
• Output pins used as the counter output

For a positive-edge-triggered counter using ~Q as the next-stage clock:

• Q outputs (Out_A) show up counting.
• ~Q outputs (Out_B) show down counting.

Fig. 3: Asynchronous Counter with Out_A counts up and Out_B counts down

Table 3: Asynchronous Counter Direction

Changing either the clock source or the output pins reverses the visible counting direction.

An asynchronous up-down counter uses a control input C to select the counting direction.

An XOR gate is placed between each flip-flop output and the clock input of the next flip-flop.

Connections

For each stage:

CLK(next) = Q ⊕ C

For positive-edge-triggered T flip-flops:

• C = 0: XOR output follows Q.
• C = 1: XOR output becomes ~Q.

Fig. 4: Asynchronous Up-Down Counter with control input C

Table 4: Direction-Control Operation

Working

When C = 0

• The XOR gates pass the Q outputs.
• Each next stage is triggered by a rising edge at Q.
• The circuit counts down.

When C = 1

• The XOR gates produce the ~Q outputs.
• Each next stage is triggered when the previous Q falls.
• The circuit counts up.

The direction control C should change only while counting is disabled and all ripple outputs are stable. Changing C can create an unwanted edge at Q ⊕ C and falsely clock the next stage.

A T flip-flop with T = 1 divides its clock frequency by two.

Connecting several T flip-flops in a ripple chain produces multiple divided frequencies.

Fig. 5: Asynchronous Frequency Divider Circuit

Table 5: Asynchronous Divider Outputs

For frequency at output Qk, where k = 0, 1, 2, ...:

fQk = fCLK / 2ᵏ⁺¹

For an n-stage counter, the frequency at last output is:

fQ(n−1) = fCLK / 2ⁿ

Working

• FF0 toggles on every clock pulse.
• FF1 toggles at half the frequency of FF0.
• Each additional stage divides the previous frequency by two.

The MOD number tells how many valid states a counter uses before repeating.

Examples:

• MOD-4 uses four states.
• MOD-6 uses six states.
• MOD-10 uses ten states.

An n-bit binary counter naturally has:

MOD = 2ⁿ

A counter with a smaller MOD value can use asynchronous PRESET and/or CLEAR inputs to redirect unwanted states to a valid state.

Design Method

1. Find the required number of states.
2. Select the required number of flip-flops.
3. Build the normal asynchronous counter.
4. Identify the first unwanted state.
5. Decode the unwanted state.
6. Use ~PRE and/or ~CLR to move the counter to a valid starting state.

Example: MOD-6 Up Counter

A 3-bit counter has eight possible states, but a MOD-6 counter requires only:

000 → 001 → 010 → 011 → 100 → 101 → 000

When the temporary state 110 appears:

• The state-decoding circuit becomes active.
• ~CLR becomes LOW.
• All flip-flops return to 000.

Fig. 6: Asynchronous MOD-6 Up Counter

Table 6: MOD-6 State Use

Invalid-State Recovery

An invalid state can be forced to a valid state by controlling each asynchronous input separately.

For example, to force 101:

• Preset the flip-flops that must become 1.
• Clear the flip-flops that must become 0.

This allows an asynchronous up or down counter to recover to the required starting state.

Flip-flop outputs in an asynchronous counter do not change at the same time.

The clock transition moves through the counter one stage at a time.

Example

During the change:

011 → 100

The outputs may briefly pass through:

011 → 010 → 000 → 100

These temporary values occur because each flip-flop has a propagation delay.

Total Delay

For an n-bit counter:

Worst-case settling delay ≈ n × flip-flop propagation delay

Effects

• Temporary incorrect states
• Decoder glitches
• Reduced maximum clock frequency
• Delayed higher-bit outputs

Asynchronous counters are simple, but they are less suitable when all output bits must change together.

In a synchronous counter, all flip-flops receive the same clock signal.

A flip-flop toggles only when all lower-order bits are HIGH.

For a 3-bit positive-edge-triggered T counter:

T0 = 1
T1 = Q0
T2 = Q1 · Q0

Fig. 7: 3-bit Synchronous Up Counter

Table 7: Synchronous Up-Counter State Table

Working

• Q0 toggles during every active clock edge.
• Q1 toggles when Q0 = 1.
• Q2 toggles when Q1Q0 = 11.
• All selected flip-flops toggle together at the active clock edge.

A synchronous down counter toggles a higher-order bit when all lower-order bits are LOW.

For a 3-bit positive-edge-triggered T counter:

T0 = 1
T1 = ~Q0
T2 = ~Q1 · ~Q0

Fig. 8: 3-bit Synchronous Down Counter

Table 8: Synchronous Down-Counter State Table

Working

• Q0 toggles during every active clock edge.
• Q1 toggles when Q0 = 0.
• Q2 toggles when Q1Q0 = 00.
• All selected outputs change together.

A synchronous up-down counter uses a control input C.

In this circuit:

• C = 1: Up counting
• C = 0: Down counting

Table 9: Synchronous Up-Down Excitation Table

Reduced Equations

T0 = 1

T1 = C · Q0 + ~C · ~Q0

This can also be written as:

T1 = ~(C ⊕ Q0)

For the third stage:

T2 = C · Q1 · Q0 + ~C · ~Q1 · ~Q0

This can also be written as:

T2 = ~(C ⊕ Q1) · ~(C ⊕ Q0)

[Image: 3-bit-synchronous-up-down-counter (common clock with C-controlled T-input logic)]

Fig. 9: 3-bit Synchronous Up-Down Counter with controlled input C

Working

When C = 1

• Lower bits are checked for HIGH.
• The circuit follows the up-counting equations.

When C = 0

• Lower bits are checked for LOW.
• The circuit follows the down-counting equations.

A synchronous MOD counter uses only the required states from the available binary states.

For M required states, select the smallest number of flip-flops n such that:

2ⁿ ≥ M

Design Method

1. List the required counting sequence.
2. Prepare the present-state and next-state table.
3. Find each T input using: T = Q ⊕ Q(next)
4. Decide how invalid states should operate.
5. Simplify the T-input equations.
6. Build the combinational logic and connect all flip-flops to a common clock.

Invalid-State Operations

Invalid states can be handled using two methods:

1.      Don’t Care Method

2.      Assigned Recovery-State Method

Table 10: Invalid-State Comparison

Don’t Care Method

• Invalid-state entries are treated as X during equation simplification.
• This reduces logic, but the counter may not recover correctly if noise or startup conditions place it in an invalid state.

Assigned Recovery-State Method

• Every invalid state is assigned a known valid next state.
• For example: Invalid State → Initial Valid State
• This makes the counter self-correcting.

MOD-11 Down Counter

A MOD-11 down counter uses eleven valid states:

10 → 9 → 8 → 7 → 6 → 5 → 4 → 3 → 2 → 1 → 0 → 10

Four T flip-flops are required because:

2³ < 11 ≤ 2⁴

Binary states 1011 to 1111 are invalid. In this design, every invalid state is redirected to 1010, which represents decimal 10.

Table 11: MOD-11 Down-Counter Excitation Table

Reduced Equations

T3 = ~Q2 · ~Q1 · ~Q0
T2 = Q2 · Q3 + ~Q1 · ~Q0 · (Q2 + Q3)
T1 = ~Q0 · (~Q2 + ~Q3) + Q2 · Q3 · ~Q1
T0 = Q0 + Q1 · ~Q2 + (Q2 ⊕ Q3)

Fig. 10: Synchronous MOD-11 Down Counter Circuit

Working

• All flip-flops receive the same positive-edge clock.
• States 1010 to 0000 form the valid down-count sequence.
• After 0000, the next state becomes 1010.
• If the circuit enters 1011 to 1111, the next clock moves it to 1010.
• ~Reset = 0 keep the circuit lock in 1010 state.

A synchronous binary up counter can also work as a frequency divider.

All flip-flops receive the same clock, but their T inputs follow the up-counter equations.

For six flip-flops:

T0 = 1
T1 = Q0
T2 = Q1 · Q0
T3 = Q2 · Q1 · Q0
T4 = Q3 · Q2 · Q1 · Q0
T5 = Q4 · Q3 · Q2 · Q1 · Q0

Fig. 11: 6-bit Synchronous Frequency Divider Circuit

Table 12: Six-Stage Divider Frequencies

Working

• Q0 toggles during every active clock edge.
• Each higher output toggles at half the frequency of the previous output.
• All selected flip-flops update from the same common clock edge.

Propagation Delay at the Outputs

The output transition does not ripple from one flip-flop to another.

• Each selected output changes after its individual flip-flop clock-to-Q delay.
• The higher-bit T-input logic must settle before the next active clock edge.
• The maximum clock frequency is limited by the flip-flop clock-to-Q delay, the longest combinational-logic delay, the setup time, and clock skew.

Minimum clock period ≈ tCQ + tlogic(max) + tsetup

A synchronous divider gives more closely aligned output transitions than an asynchronous divider.

A custom sequence generator is a synchronous counter that follows a user-defined order instead of normal binary up or down counting.

Example:

State A → State B → State C → State A

Design Method

1. Write the required state sequence.
2. Map each present state to its next state.
3. Find the T inputs using: T = Q ⊕ Q(next)
4. Prepare the excitation table.
5. Simplify the T-input equations.
6. Build the combinational logic.
7. Connect all flip-flops to a common clock.

Table 13: Custom Sequence Mapping

Custom Sequence Example

The required sequence is:

000 → 110 → 010 → 101 → 111 → 100 → 011 → 001 → 000

This sequence uses all eight possible 3-bit states.

Table 14: Custom Sequence Excitation Table

Reduced Equations

T2 = ~Q0
T1 = ~(Q2 ⊕ Q0) + (Q2 ⊕ Q1)
T0 = Q2 ⊕ Q1 ⊕ Q0

Fig. 12: Custom Sequence Generator using T Flip Flops

Working

• All three T flip-flops receive the same clock.
• The combinational circuit calculates T2, T1, and T0.
• At each positive clock edge, the counter moves to the next specified state.
• After 001, the sequence returns to 000.