56. Control Flow Basics

When compiling this Verilog module through standard RTL logic synthesis, what occurs?

module dynamic_loop(input [3:0] limit, input [7:0] data, output reg y);
    integer i;
    always @(*) begin
        y = 0;
        for (i = 0; i < limit; i = i + 1) begin
            y = y ^ data[i];
        end
    end
endmodule