51. 4-Bit Modular Adder Block

• Output Sum Analysis: For the first bit (S0), the sum uses just one XOR gate because there is no previous carry to worry about. For the next bits (S1, S2, S3), the circuit uses two XOR gates in a row to add the two input bits plus the carry coming from the previous stage.
• Output Carry Analysis: The first carry bit (C1) is built using a single AND gate. For the next stages, a carry-out is created whenever any two or three inputs are turned on. To keep the circuit small, the logic reuses the math from the first XOR gate instead of building a new path from scratch.
• Hardware Optimization: The circuit links four separate single-bit adding stages together. The carry-out from each lower stage connects directly into the carry-in of the next higher stage, allowing the carry bit to pass along like a ripple from the first bit (S0) all the way to the final Cout.

Boolean Equations:

• Stage 0 (First Bit):
  • S0 = A0 ^ B0
  • C1 = A0 . B0
• Stages n (1 to 3):
  • Sn = (An ^ Bn) ^ Cn
  • Cn+1 = (An . Bn) + (Cn . (An ^ Bn))
  • (Note: C4 is the final Cout)