40. 4-to-1 Data Selector

The output of a combinational circuit changes whenever its input combination changes, after the circuit's propagation delay. 

Design flow: requirement → Truth Table → Boolean Expression → Simplified Circuit → Verification 

• Use a truth table to describe required input-to-output behaviour. 

• Use Boolean algebra or a K-map to simplify the logic. 

• Use MUXs, DEMUXs, decoders, encoders, and gates as reusable building blocks. 

• Verify both normal operation and control-signal conditions such as enable and active-low inputs. 

A multiplexer is a controlled digital selector. Its select lines choose one data input and connect that input to the single output. 

Signal flow: 2^n data inputs + n select lines → MUX → Y 

Working 

• The binary value on the select lines identifies the selected input index k. 

• The output follows only that input: Y = Dk. 

• Changes on unselected inputs do not affect Y while the selection remains unchanged. 

• The input-to-select-code order must be checked from the circuit or datasheet; never assume the bit order. 

Using a MUX to implement logic 

1. Connect chosen function variables to the select lines. 

2. Evaluate the required function for every select combination. 

3. Connect each data input to 0, 1, another signal, or its complement as required. 

4. Verify every select state against the required function. 

Cascading MUXs 

Smaller MUXs can be connected in stages to create a wider data selector. Cascading increases design size and adds propagation delay through each stage. 

Always check the select-bit distribution, enable behaviour, and total propagation delay when MUXs are cascaded. 

A demultiplexer is a controlled digital distributor. It sends one data input to one selected output while keeping the other outputs inactive. 

Signal flow: D + Select Lines → DEMUX → One Selected Output 

Working 

• The select code identifies the destination output index k. 

• The selected output follows the input: Yk = D. 

• The other active-HIGH outputs remain LOW. 

• If D is LOW, all active-HIGH outputs are LOW even though a destination is selected. 

A DEMUX answers “Where should this data go?” A decoder answers “Which control line should be active?” A DEMUX includes a data input; a decoder normally uses only a binary code and control inputs. 

A decoder converts an n-bit binary code into one active output among 2^n output lines. It is useful for address selection, control generation, and one-hot state selection. 

Signal flow: n-bit code + Enable → Decoder → One-hot output lines 

Working and enable 

• Each output represents one possible input code. 

• With an active-HIGH decoder, the selected output becomes HIGH. 

• With an active-LOW decoder, the selected output becomes LOW. 

• An enable input can allow or block all decoder outputs. 

• Always identify the output polarity before connecting it to another circuit. 

For an active-HIGH decoder, the selected output can be described generally as: 

Yk = minterm corresponding to input code k 

For active-LOW control lines, the output is usually inverted after the selection logic. 

The selected line is LOW; inactive lines are HIGH. 

An encoder performs the reverse operation of a decoder. It converts an active input line into its binary position code. 

Signal flow: One-hot Input Lines → Encoder → Binary code + Valid status 

Working conditions 

• A basic encoder assumes that only one input is active. 

• The binary output identifies the active input position. 

• A valid output indicates whether at least one input is active. 

• When no input is active, the code may be unspecified; use the valid signal before interpreting it.  

For active-HIGH inputs, the valid signal is the OR of all input lines: 

V = I0 + I1 + I2 + ... + Im 

Priority Encoder 

A priority encoder extends an encoder so that multiple active inputs are handled according to a fixed priority order. 

Signal flow: multiple request lines → priority logic → highest-priority code + V 

• The priority rule must be defined explicitly, such as highest index first or lowest index first. 

• The output code represents the highest-priority active input. 

• V = 0 means that no request is active. 

• When V = 0, the encoded output is normally treated as invalid or don't-care. 

• Priority logic prevents a lower-priority request from changing the output while a higher-priority request is active. 

  

Parity adds one bit to a data word so that the total number of HIGH bits follows an even- or odd-parity rule. 

Signal flow: Data bits → XOR network → Parity bit 

For data bits D0 through Dm: 

• Even-parity bit: P = D0 ⊕ D1 ⊕ ... ⊕ Dm 

• Odd-parity bit: P = ~(D0 ⊕ D1 ⊕ ... ⊕ Dm) 

At the receiver, XOR the data bits with the received parity bit. The result indicates whether the required parity condition is satisfied. Parity can detect many single-bit errors, but it cannot identify the faulty bit or correct the data. 

• Wrong MUX result: check select-bit order, input indexing, and complementary select paths. 

• DEMUX output inactive: check the data input, selected destination, enable state, and output polarity. 

• Decoder selects the wrong line: check binary-code order and active-HIGH or active-LOW behaviour. 

• Encoder code is unreliable: ensure the one-hot assumption is valid or use a priority encoder. 

• Priority output is unexpected: verify the stated priority direction and the valid signal. 

• Parity check fails: confirm whether even or odd parity is required and include the parity bit in the check. 

• Circuit is slow: count cascaded gate or MUX stages and account for their combined propagation delay. 

• Unspecified output is being used: check the valid or enable signal before interpreting a code. 

Remember: a MUX chooses, a DEMUX distributes, a decoder activates, an encoder codes, a priority encoder resolves, parity checks.