35. AND Primitive

module and2_prim (
    input  a,
    input  b,
    output y
);
    and g_and (y, a, b);
endmodule

💡Remember

Gate primitives (and, or, nand, …) are built-ins—no sensitivity lists, purely structural.
They follow Verilog’s 4-state truth table (e.g., 1 & x -> x, 0 & x -> 0).