28. AND Primitive

module and2_prim (
    input  a,
    input  b,
    output y
);
    and g_and (y, a, b);
endmodule
💡Remember
Gate primitives (and, or, nand, …) are built-ins—no sensitivity lists, purely structural.
They follow Verilog’s 4-state truth table (e.g., 1 & x -> x, 0 & x -> 0).

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Testbench Code

`timescale 1ns/1ps

module tb_and2_prim;
    // 1) Inputs
    reg a, b;

    // 2) DUT outputs
    wire y;

    // 3) Expected (prefixed expected_)
    reg expected_y;

    // 4) Mismatch (HIGH on fail)
    reg  mismatch;
    wire mismatch_w = (y !== expected_y);

    // Accounting
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // VCD limit (record at most 32 cases)
    integer VCD_MAX_CASES = 32;

    // DUT
    and2_prim dut(.a(a), .b(b), .y(y));

    // VCD dump (Inputs -> Outputs -> Expected -> Mismatch)
    initial begin
        $dumpfile("tb_and2_prim.vcd");
        $dumpvars(0,
            tb_and2_prim.a, tb_and2_prim.b,  // Inputs
            tb_and2_prim.y,                  // Output
            tb_and2_prim.expected_y,         // Expected
            tb_and2_prim.mismatch            // Mismatch
        );
        $dumpon; // start at time 0
    end

    // Init + header
    initial begin
        a = 1'b0; b = 1'b0; mismatch = 1'b0; expected_y = 1'b0;
        $display(" a  b | y | expected_y | mismatch");
        $display("-------------------------------");
    end

    // Apply + check (EXPECTED FIRST -> WAIT -> COMPARE)
    task apply_and_check;
        input ta, tb;
        begin
            a = ta; b = tb;

            // Compute expected first (4-state bitwise &)
            expected_y = (ta & tb);

            #1; // let DUT settle
            mismatch = mismatch_w;

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch) TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            else           TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;

            $display(" %s  %s | %s |     %s     |    %0d",
                     bit2s(a), bit2s(b), bit2s(y), bit2s(expected_y), mismatch);

            if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
        end
    endtask

    // Helper to print 4-state bits nicely
    function [7*8-1:0] bit2s; // up to "1", "0", "x", "z"
        input bitval;
        begin
            if      (bitval === 1'b0) bit2s = "0";
            else if (bitval === 1'b1) bit2s = "1";
            else if (bitval === 1'bx) bit2s = "x";
            else                      bit2s = "z";
        end
    endfunction

    integer i;
    initial begin
        // Full truth table for 0/1 (4 lines)
        apply_and_check(1'b0, 1'b0);
        apply_and_check(1'b0, 1'b1);
        apply_and_check(1'b1, 1'b0);
        apply_and_check(1'b1, 1'b1);

        // A few X/Z robustness cases
        apply_and_check(1'bx, 1'b0); // -> 0
        apply_and_check(1'b0, 1'bx); // -> 0
        apply_and_check(1'b1, 1'bx); // -> x
        apply_and_check(1'bx, 1'b1); // -> x
        apply_and_check(1'bz, 1'b1); // -> x (z treated as unknown)
        apply_and_check(1'b1, 1'bz); // -> x

        // Summary
        $display("-------------------------------");
        $display("TOTAL_TEST_CASES=%0d", TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule