17. Binary to Gray Code Converter

How do you plan to solve it?

don't make mistake of writing length of ports after declaring its name 

bin_in[3:0] is wrong; works in svv not in verilog;

correct way is [3:0]bin_in;

/*Write your code here*/
module bin2gray4(input [3:0] bin_in,output [3:0] gray_out);
 assign gray_out[3]=bin_in[3]; 
 assign gray_out[2]=bin_in[3]^bin_in[2]; 
 assign gray_out[1]=bin_in[2]^bin_in[1]; 
 assign gray_out[0]=bin_in[1]^bin_in[0]; 
endmodule