16. Parking Lot Status

Design a Verilog module that reports parking lot status for a 16-bit occupancy map. Each bit of the input indicates whether a slot is occupied (1) or free (0).

Requirements

• Module name: parking_status16
• Inputs:
  • slots[15:0] — bit i represents slot i (1 = occupied, 0 = free)
• Outputs:
  • all_full — 1 when every slot is occupied
  • any_free — 1 when at least one slot is free

Expected behaviour