How do you plan to solve it?
module bin2gray4 ( input[3:0] bin_in , output[3:0] gray_out ); genvar i; generate for(i = 0 ; i < 3 ; i = i + 1) assign gray_out[i] = bin_in[i] ^ bin_in[i+1]; endgenerate assign gray_out[3] = bin_in[3] ; endmodule