How do you plan to solve it?
module bin2gray4( input [3:0]bin_in, output reg [3:0]gray_out ); //assign gray_out = bin_in ^ bin_in>>1; integer i; always@(*) begin for(i=2; i>=0; i = i-1) begin gray_out[i] <= bin_in[i] ^ bin_in[i+1]; end gray_out[3] <= bin_in[3]; end endmodule