/*Write your code here*/
module bin2gray4(
input wire [3:0] bin_in,
output wire [3:0] gray_out
);
genvar i;
generate
for(i = 3; i >= 0; i = i - 1)begin
if(i == 3)begin
assign gray_out[i] = bin_in[i];
end
else begin
assign gray_out[i] = bin_in[i + 1] ^ bin_in[i];
end
end
endgenerate
endmodule;