How do you plan to solve it?
/*Write your code here*/ module bin2gray4 ( input wire [3:0] bin_in, output reg [3:0] gray_out ); integer i; always@* begin gray_out[3]=bin_in[3]; for(i=2;i>=0;i=i-1) gray_out[i]=bin_in[i+1]^bin_in[i]; end endmodule