How do you plan to solve it?
/*Write your code here*/ module bin2gray4(input [3:0]bin_in,output reg [3:0] gray_out); always@(*) begin gray_out[3] = bin_in[3]; gray_out[2] = bin_in[3]^bin_in[2]; gray_out[1] = bin_in[2]^bin_in[1]; gray_out[0] = bin_in[1]^bin_in[0]; end endmodule