How do you plan to solve it?
module bin2gray4 #(parameter W=4)( input [W-1:0] bin_in, output reg [W-1:0]gray_out); integer i; always@(*) begin gray_out[W-1]=bin_in[W-1]; for(i=W-2;i>=0;i--) begin gray_out[i]=bin_in[i]^bin_in[i+1]; end end endmodule